Project 2.1: ALU and Regfile
Project 1.2 Project 2.1 Project 2.2
Overview | Deliverables | Logisim | Testing | Submission
Overview
- MAKE SURE TO CHECK YOUR CIRCUITS WITH THE GIVEN HARNESSES TO SEE IF THEY FIT! YOU WILL FAIL ALL OUR TESTS IF THEY DO NOT.
(This also means that you should not be moving around given inputs and outputs in the circuits). - This is a PARTNER project. Use the gradebot repositories accordingly!
- Sample tests for a completed ALU and Regfile have been included in the proj2-1StartKit. Given the current directory structure, you can run the bash script (short-test.sh) with your *.circ files in the same directory and it will run the autograder. We recommend running the sample tests locally, but the autograder only works with python 2.7. These tests are NOT comprehensive, you will need to do further testing on your own.
- You are allowed to use any of Logisim's built-in blocks for all parts of this project.
- Save often. Logism can be buggy and the last thing you want is to lose some of your hard work.
In this project you will be using MIPS-Logisim to create a 32-bit two-cycle processor. It is similar to MIPS, except that memory addresses represent 32-bit words instead of 8-bit bytes (word-addressed instead of byte-addressed). Also, all addresses are 24-bits wide instead of 32-bits, due to limitations in Logisim. Throughout the implementation of this project, we'll be making design choices that make it compatible with machine code outputs from MARS and your Project 1!
Please read this document CAREFULLY as there are key differences between the processor we studied in class and the processor you will be designing for this project.
Overview | Deliverables | Logisim | Testing | Submission
Deliverables
Approach this project like you would any coding assignment: construct it piece by piece and test each component early and often!
Tidyness and readability will be a large factor in grading your circuit if there are any issues, so please make it as neat as possible! If we can't comprehend your circuit, you will probably receive no partial credit.
1) Obtaing the Files
Similarly to project 1, we will be distributing the project files through git. You can look back on the step 0 for project 1 for more specific steps.
- In the repository add a remote repo that contains the framework files:
git remote add framework http://shtech.org/course/ca/projects/proj2.1.git - Go and fetch the files:
git fetch framework - Now merge those files with your master branch:
git merge framework/master - The rest of the git commands work as usual.
2) Register File
Although our ISA promises the whole range of 32 registers, we will provide you with access to 28 registers in Project 2.2. Your task is to implement 4 more - $t0, $t1, $t2, and $t3. After being told to write data to one of these 4 registers, you should be able to retrieve that data by asking for the value of that register on subsequent clock cycles.
You are provided with the skeleton of a register file in regfile.circ. The register file circuit has six inputs:
Input Name | Bit Width | Description |
CLK | 1 | Input for the clock. This can be sent into subcircuits or attached directly to the clock inputs of memory units in Logisim, but should not otherwise be gated (i.e., do not invert it, do not and it with anything, etc.). |
RegWrite | 1 | Determines whether data is written on the next rising edge of the clock. |
Read Register 1 | 2 | Determines which register's value is sent to the Read Data 1 output, see below. |
Read Register 2 | 2 | Determines which register's value is sent to the Read Data 2 output, see below. |
Write Register | 2 | Determines which register to set to Write Data on the next rising edge of the clock, assuming that RegWrite is asserted. |
Write Data | 32 | Determines what data to write to the register identified by the Write Register input on the next rising edge of the clock, assuming that RegWrite is asserted. |
The register file also has the following six outputs:
Output Name | Bit Width | Description |
$t0 Value | 32 | Always driven with the value of $t0. This is primarily for grading & debugging; if you were really designing a register file you would probably omit this output. |
$t1 Value | 32 | Always driven with the value of $t1. This is primarily for grading & debugging; if you were really designing a register file you would probably omit this output. |
$t2 Value | 32 | Always driven with the value of $t2. This is primarily for grading & debugging; if you were really designing a register file you would probably omit this output. |
$t3 Value | 32 | Always driven with the value of $t3. This is primarily for grading & debugging; if you were really designing a register file you would probably omit this output. |
Read Data 1 | 32 | Driven with the value of the register identified by the Read Register 1 input. |
Read Data 2 | 32 | Driven with the value of the register identified by the Read Register 2 input. |
You can make any modifications to regfile.circ you want, but the outputs must obey the behavior specified above. In addition, your regfile.circ that you submit must fit into the regfile-harness.circ file we have provided for you. This means that you should take care to not reorder inputs or outputs, though you can move them around if you need more space or something. A circuit like regfile-harness.circ will be used to test your register file for grading. You should download a fresh copy of regfile-harness.circ and make sure your regfile.circ is cleanly loaded before submitting.
3)Arithmetic Logic Unit (ALU)
The ALU for this project is very similar to the one you made in lab. The most important differences are:
- Instead of a 3 bit control signal, we are using the 6 bit funct field from the instruction.
An issue that you will run into is that a mux can only have a max of 5 selector bits.
You will need to figure out how to properly select the correct instructions.
Hint: There is a way for you use only one mux. - We will have a signal that is true iff X and Y are equal.
- We will have a signal that is on when there is a signed overflow. For a refresher on signed overflow follow the link here.
You will tell your ALU what operation to perform and it will drive its output with the result of that operation. You ARE allowed to use all of Logisim's built-in arithmetic blocks, including adder, subtractor, and shifter. Alternatively, feel free to use any sub-circuit that you created previously for homework or lab.
We have provided a skeleton of an ALU for you in alu.circ. It has three inputs:
Input Name | Bit Width | Description |
X | 32 | Data to use for X in the ALU operation. |
Y | 32 | Data to use for Y in the ALU operation. |
Switch(S) | 6 | Selects what operation the ALU should perform (see below). |
The ALU also has three outputs:
Output Name | Bit Width | Description |
Signed Overflow | 1 | High iff the operation was an add or sub and there was signed overflow. |
Result | 32 | Result of the ALU Operation. |
Equal | 1 | High iff the two inputs X and Y are equal. |
The funct code for each instruction should be the same as specified in the MIPS Green Sheet, and are reproduced below. In addition, you should implement the following two new instructions:
funct(hex) | Instruction |
00 | sll: result = X << Y |
02 | srl: result = X >> Y (zero-extended) |
03 | sra: result = X >> Y (sign-extended) |
20 | add: result = X + Y |
21 | addu: result = X + Y |
22 | sub: result = X - Y |
23 | subu: result = X - Y |
24 | and: result = X & Y |
25 | or: result = X | Y |
2a | slt: result = (X < Y) ? 1 : 0 Signed |
2b | sltu: result = (X < Y) ? 1 : 0 Unsigned |
3e | bitpal: result = (X[31:16] == X[0:15]) ? 1 : 0 |
3f | lfsr: result = See below |
Note: You can assume for shift operations that Y will be non-negative and have a value less than 32.
Note: bitpal reverses the order of the 0-15 bits when checking for equality.
Note: The operation for lfsr should be performed on the X input.
Bit Palindrome and LFSR
We have introduced some new instructions for you to implement
The first instruction is Bit Palindrome. Here are the specifications for the instruction:
- It is an R-type instruction with a funct code of 62.
- It takes the value in $rs and checks to see if it is a palindrome or not.
- For example, the bit pattern 101101 is a palindrome, while the bit pattern 100111 is not.
- If the value in $rs is a palindrome, then a value of 1 will be put in $rd.
- If it is not a palindrome then 0 will be put in $rd
The next instruction is LFSR. Here are the specifications for the instruction:
- It is an R-type instruction with a funct code of 63.
- It takes the value in $rs and finds the next LFSR pattern. See exercise 2 from here and here for further explanations.
- The calculated LFSR pattern will then be stored in $rd
Follow the same instructions as the register file regarding rearranging inputs and outputs of the ALU. In particular, you should ensure that your ALU is correctly loaded by a fresh copy of alu-harness.circ before you submit.
Overview | Deliverables | Logisim | Testing | Submission
Logisim Notes
While you may use Logisim 2.7.1 for developing your alu.circ, regfile.circ, mem.circ, and cpu.circ, do note that you have to open run.circ with the MIPS-logisim file we provided.
If you are having trouble with Logisim, RESTART IT and RELOAD your circuit! Don't waste your time chasing a bug that is not your fault. However, if restarting doesn't solve the problem, it is more likely that the bug is a flaw in your project. Please post to Piazza about any crazy bugs that you find and we will investigate.
Things to Look Out For
- Do NOT gate the clock! This is very bad design practice when making real circuits, so we will discourage you from doing this by heavily penalizing your project if you gate your clock.
- BE CAREFUL with copying and pasting from different Logisim windows. Logisim has been known to have trouble with this in the past.
- When you import another file (Project --> Load Library --> Logisim Library...), it will appear as a folder in the left-hand viewing pane. The skeleton files should have already imported necessary files.
- Changing attributes before placing a component changes the default settings for that component. So if you are about to place many 32-bit pins, this might be desireable. If you only want to change that particular component, place it first before changing the attributes.
- When you change the inputs & outputs of a sub-circuit that you have already placed in main, Logisim will automatically add/remove the ports when you return to main and this sometimes shifts the block itself. If there were wires attached, Logisim will do its automatic moving of these as well, which can be extremely dumb in some cases. Before you change the inputs and outputs of a block, it can sometimes be easier to first disconnect all wires from it.
- Error signals (red wires) are obviously bad, but they tend to appear in complicated wiring jobs such as the one you will be implementing here. It's good to be aware of the common causes while debugging:
Logisim's Combinational Analysis Feature
Logisim offers some functionality for automating circuit implementation given a truth table, or vice versa. Though not disallowed (enforcing such a requirement is impractical), use of this feature is discouraged. Remember that you will not be allowed to have a laptop running Logisim on the final.
Overview | Deliverables | Logisim | Testing | Submission
Testing
For this part, we have provided you with a bash script called short-test.sh in the project directory as well as a few test files in test-files. Running short-test.sh will copy your alu and regfile into the test files directory and run the autograder with the two ALU tests and one Regfile test. Keep in mind that these tests are not comprehensive, so take a look at how ALU-addu.circ and reg-insert.circ are created to see how you can make your own.
Note: the autograder only works with python 2.7, so it may be easier to run it remotely off of the hive* servers if you haven't set up your python environments.
Overview | Deliverables | Logisim | Testing | Submission
Submission
Gradinscripts in the gradebot will be added later. But you can already use your group account in gradebot to conveniently share code with your partner.