Project 1.2: RVC instructions to RISC-V instructions in RISC-V

Computer Architecture I ShanghaiTech University
Project 1.1 Project 1.2 Project 2.1

IMPORTANT INFO - PLEASE READ

The projects are part of your design project worth 2 credit points. As such they run in parallel to the actual course. So be aware that the due date for project and homework might be very close to each other! Start early and do not procrastinate.

Introduction

In project 1.2, you will implement a translator that converts 16-bit RISC-V Compressed (RVC) instructions to equivalent 32-bit RISC-V instructions. Instructions are provided and output in binary form. This project is easy if you gain sufficient understanding of RISC-V from the courses, Lab 3, Lab 4 and its compressed instruction set extension from Project1.1.

To simplify the implementation, all RVC instructions map to a single existing RISC-V instruction. In this project, you only need to translate part of RVC instructions that are mentioned in Project 1.1. The instruction set is listed below.

The Instruction Set

RVC
INSTR
FORMATRISC-V
EQUIVALENT
FORMATOPFUNCT3FUNCT7
c.addCRadd rd, rd, rs2R01100110000000000
c.mvCRadd rd, x0, rs2R01100110000000000
c.jrCRjalr x0, 0 (rs1)I1100111000 
c.jalrCRjalr x1, 0 (rs1)I1100111000 
c.liCIaddi rd, x0, immI0010011000 
c.luiCIlui rd, nzimmU0110111  
c.addiCIaddi rd, rd, nzimmI0010011000 
c.slliCIslli rd, rd, shamtI00100110010000000
c.lwCLlw rd', offset (rs1')I0000011010 
c.swCSsw rs2', offset (rs1')S0100011010 
c.andCAand rd', rd', rs2'R01100111110000000
c.orCAor rd', rd', rs2'R01100111100000000
c.xorCAxor rd', rd', rs2'R01100111000000000
c.subCAsub rd', rd', rs2'R01100110000100000
c.beqzCBbeq rs1', x0, offsetSB1100011000 
c.bnezCBbne rs1', x0, offsetSB1100011001 
c.srliCBsrli rd', rd', shamtI00100111010000000
c.sraiCBsrai rd', rd', shamtI00100111010100000
c.andiCBandi rd', rd', immI0010011111 
c.jCJjal x0, offsetUJ1101111  
c.jalCJjal x1, offsetUJ1101111  

Although some of the RVC instruction can be expanded in different ways, we suggest you to follow the above translation or you will fail some testcases.

Instruction Formats

A detailed description of compressed instruction formats is provided for you. You can either refer to The RISC-V Instruction Set Manual, Chapter 16, or The RISC-V Compressed Instruction Set Manual Version 1.9. If there are any mistakes below, the document would prevail.

CR Format

CRfunct4rd/rs1rs2opcode
Bits4552
C.ADD1001dest≠ 0src≠ 010
C.MV1000dest≠ 0src≠ 010
C.JR1000src≠ 0010
C.JALR1001src≠ 0010

CI Format

CIfunct3immrd/rs1immopcode
Bits31552
C.LI010imm[5]dest≠ 0imm[4:0]01
C.LUI011nzimm[17]dest≠{0,2}nzimm[16:12]01
C.ADDI000nzimm[5]dest≠ 0nzimm[4:0]01
C.SLLI000shamt[5]dest≠ 0shamt[4:0]10

CL Format

CLfunct3immrs1'immrd'opcode
Bits333232
C.LW010offset[5:3]baseoffset[2|6]dest00

CS Format

CSfunct3immrs1'immrs2'opcode
Bits333232
C.SW110offset[5:3]baseoffset[2|6]src00

CA Format

CAfunct6rd'/rs1'funct2rs2'opcode
Bits63232
C.AND100011dest11src01
C.OR100011dest10src01
C.XOR100011dest01src01
C.SUB100011dest00src01

CB Format

CB-TYPE1funct3immrd'/rs1'immopcode
Bits33352
C.BEQZ110offset[8|4:3]srcoffset[7:6|2:1|5]01
C.BNEZ111offset[8|4:3]srcoffset[7:6|2:1|5]01
CB-TYPE2funct3immfunct2rd'/rs1'immopcode
Bits312352
C.SRLI100shamt[5]00destshamt[4:0]01
C.SRAI100shamt[5]01destshamt[4:0]01
C.ANDI100imm[5]10destimm[4:0]01

CJ Format

CJfunct3Jump targetopcode
Bits3112
C.J101offset[11|4|9:8|10|6|7|3:1|5]01
C.JAL001offset[11|4|9:8|10|6|7|3:1|5]01

And recall the RV32 instrcution formats which has been covered in the lecture. The necessary knowledge for the project is provided below. You can either consult The RISC-V Instruction Set Manual, Chapter 2, or RISC-V Green Card for further information.

R Format

Rfunct7rs2rs1funct3rdopcode
Bits755357

I Format

Iimm[11:0]rs1funct3rdopcode
Bits125357

S Format

Simm[11:5]rs2rs1funct3imm[4:0]opcode
Bits755357

SB Format

SBimm[12]imm[10:5]rs2rs1funct3imm[4:1]imm[11]opcode
Bits16553417

U Format

Uimm[31:12]rdopcode
Bits2057

UJ Format

UJimm[20]imm[10:1]imm[11]imm[19:12]rdopcode
Bits1101857

Registers

In compressed RISC-V, Format CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them. The following table lists these popular registers specified by the three-bit rs1',rs2', and rd' fields of these formats, which correspond to RISC-V integer registers x8 to x15.

RVC REGISTER NUMBER000001010011100101110111
INTEGER REGISTER NUMBERx8x9x10x11x12x13x14x15

Implementation

Here is a simple template to begin with.

Input

A reference input is already provided to you in the input.S file. The final tests's input have the same format as the provided input except the number and contents of RVC codes.


.data

# Constant integer specifying the lines of RVC codes

# DO NOT MODIFY THIS VARIABLE
.globl lines_of_rvc_codes
lines_of_rvc_codes:
    .word 7


# RVC codes, 16-bits instructions mixed with 32-bits instructions
# A 16/32-bits binary number represents one line of rvc code.
# You can suppose all of the input codes are valid.

# DO NOT MODIFY THIS VARIABLE
.globl rvc_codes
rvc_codes:
    .word 0b00000000000000000000001010110011
    .half 0b0001010111111101
    .half 0b1001001010101010
    .half 0b0001010111111101
    .word 0b11111110000001011101111011100011
    .half 0b1000010100010110
    .half 0b1000000010000010

Hint

Output

In this project, you need to output the results in binary form. For input.S, the output should be:


00000000000000000000001010110011
11111111111101011000010110010011
00000000101000101000001010110011
11111111111101011000010110010011
11111110000001011101110011100011
00000000010100000000010100110011
00000000000000001000000001100111

Exited with error code 0

It's usually the duty of the supervisor (operating system) to deal with input/output and halting program execution. Venus, being a simple emulator, does not offer us such luxury, but supports a list of primitive environmental calls. Since Venus does not provide an environmental call to directly print binary, you may need to combine some of the environmental calls to achieve the above output. The following environmental calls could be helpful.

ID (a0)NameDescription
1print_intprints integer in a1
11print_characterprints ASCII character in a1
17exit2ends the program with return code in a1

The command that we use to test your program's correctness is

diff <your_transformed_output> <reference_output>

You can also test your result using this command.

Execution

Make sure that venus-jvm-latest.jar, translator.S and input.S reside in the same directory. To run your program locally and write the output to translator.output, use the following command.

java -jar venus-jvm-latest.jar translator.S >> translator.output

To debug your program online, you might want to replace .import input.S in translator.S with the content of input.S.

Tips

Submission