Computer Architecture

Spring 2020

School of Information Science and Technology SIST
SchanghaiTech University

LectureTuesday, 10:15-11:55. 教学中心 (Teaching Center) 201
LectureThursday, 10:15-11:55. 教学中心 (Teaching Center) 201
Discussionstbd.
Lab 1Monday, 15:55-17:35. SIST 1D-104; TA: Ze Song
Lab 2Tuesday, 19:35-21:15. SIST 1D-104; TA: Zhongyi Cai
Lab 3Tuesday, 19:35-21:15. SIST 1D-108; TA: Kaiyuan Xu
Lab 4Tuesday, 15:55-17:35. SIST 1A-104; TA: Tianyuan Wu
Lab 5Tuesday, 15:55-17:35. SIST 1A-106; TA: Peifan Li
Lab 6Tuesday, 15:55-17:35. SIST 1A-108; TA: Mengying Wu
Lab 7Tuesday, 19:35-21:15. SIST 1A-104; TA: Cheng Yu
Lab 8Tuesday, 19:35-21:15. SIST 1A-106; TA: Peihao Wang
Lab 9Tuesday, 19:35-21:15. SIST 1A-108; TA: Zhongyue Lin
ForumPost all your questions on the forum.
AutolabSubmit your homework and projects to autolab.
GradescopeSome homework and exames will be available on gradescope.
Schedule
Week Date Topic Video Reading Discussion Homework Lab Project
1 03-03 Introduction (PDF) P&H: 2.4 Discussion 1 HW 1 on Autolab!
Due: Fri., Mar. 6
No Lab
03-05 Intro to C I (PDF) K&R: 1-6
2 03-10 Intro to C II (PDF) K&R: 7-8, App. A & B Discussion 2 HW 2
Due Thur., Mar. 12
Lab 1
03-12 RISC-V Intro (PDF) P&H: 2.1 - 2.3 Discussion 3
3 03-17 RISC-V Decisions (PDF) P&H: 2.6, 2.7, 2.9, 2.10 HW 3
Due Fri., Mar. 27
Lab 2 Project 1.1
Due Fri., April 3
03-19 RISC-V Instruction Formats (PDF) P&H: 2.5, 2.10 Discussion 4
4 03-24 Compiler, Assembler, Linker, Loader (CALL) (PDF) P&H: 2.12 Discussion 5 HW 4
Due Fri., Apr. 10
Solution
Lab 3
03-26 Intro to Synchronous Digital Systems (SDS), Logic (PDF) P&H: A.2, A.3 Discussion 6
5 03-31 Functional Units, FSM (PDF) P&H: A.3 - A.6 Lab 4 Project 1.2
Due Tue., April 14
04-02 RISC-V Datapath (PDF) P&H: 4.1, 4.2, 4.3 Discussion 8
6 04-07 RISC-V Single-Cycle Control (PDF) P&H: 4.4 HW 5
Due Tue., Apr. 21
Lab 5
04-09 RISCV 5-Stage Pipeline/Hazards (PDF) P&H: 4.5 - 4.9
7 04-14 Superscalar (PDF) P&H: 4.10, 4.11 Discussion 10 Lab 6 Project 2.1
Due Thu., April 30
04-16 Memory Hierarchy, Fully Associative Caches (PDF) P&H: 5.1, 5.2, 5.3, 5.4
8 04-21 Caches: Direct-mapped, Set-associative, Program Performance with Caches (PDF) P&H: 5.1, 5.2, 5.3, 5.4, 5.8, 1.6 Discussion 12 HW 6
Due Wed., May. 6
Solution
Lab 7
04-23 Multilevel Caches, Cache Questions (PDF) P&H: 5.1, 5.2, 5.3, 5.4, 5.8, 1.6
9 04-28 Performance, Floating Point (PDF) P&H: 3.5, 3.9 Discussion 13 Lab 8 Project 2.2
Due Tue., May 12
04-30 Flynn Taxonomy, Data-Level Parallelism (PDF) P&H: 1.7, 1.8, 4.10, 4.11, 6.1, 6.2, 6.3, 6.7
1005-07 Thread-Level Parallelism, OpenMP Intro (PDF) P&H: 2.11, 5.10, 6.4, 6.5 No Lab
05-09 Cache Coherence, OpenMP Sharing Issues (PDF) P&H: 2.11, 4.10, 5.10, 6.4, 6.5
1105-12 OS Support, Base and Bounds, Interrupts, Virtual Memory Intro (PDF)
(Online Lecture: More VM)
P&H: 5.13, 5.15, 5.16 Discussion 17 HW 7
Due Fri., Jun. 5
Lab 9 Project 3
Due Sat., May 30
05-14 More Virtual Memory (PDF)
(Online Lecture: Advanced $)
P&H: 6.9, 4.9 Discussion 18
12 05-19 Advanced Caches (PDF)
(Online Lecture: Review & Summary)
P&H: 5.12, 5.13, 5.15 Lab 10
05-21 Review & Summary Midterm (PDF)
(Online Q&A)
13 05-26 Midterm No Lab Midterm Page 1
Midterm
Midterm Solution
05-28 Online Lecture: FPGA (PDF)
14 06-02 FPGA
(Online Lecture: Warehouse Scale Computing, MapReduce, Spark) (PDF)
P&H: A.12 FPGA Lab 11 Project 4
Due Sun., June 28
06-04 Warehouse Scale Computing, MapReduce, Spark (Online Lecture: I/O: DMA, Disks, Networking) (PDF) P&H: 6.7
15 06-09 I/O: DMA, Disks, Networking (Online Lecture: Dependability: Parity, ECC, RAID) (PDF)
  • V1 Availability
  • V2 Hamming_ECC
  • V3 RAID
  • P&H: 5.1, 5.2, 6.9 Lab 12
    06-11 Dependability: Parity, ECC, RAID (Online Lecture: Security) (PDF)
  • V1 Security I
  • V2 Security II
  • V3 Security III
  • P&H: 5.2, 5.5, 5.11, A.9
    16 06-16 Security (Online Lecture: Final Review & Summary)
  • V1 Admin
  • V2 WSC to CPUs
  • V3 CPUs to Trans.
  • Meltdown & Spectre Lab 13
    06-18 Summary (PDF)
    (Online Q&A Final)
    P&H: all
    17June 23 Final 8am - 10am Final p1
    Final
    Final Solution
    18June 29 & 30 Checkup Lab Project 4 checkup
    Instructor
    Sören Schwertfeger
    Sören Schwertfeger 师泽仁
    <soerensch>
    OH: You are always welcome! Wed. 10:00-15:00; Room: 1D 201.A
    Chundong Wang
    Chundong Wang
    <wangchd>
    OH: tbd.

    TAs
    Please check the TA office hours on piazza.
    Yanjie Song
    Yanjie Song
    <songyj>
    Head TA
    Anqi Pang
    Anqi Pang
    <pangaq>
    Cheng Yu
    Cheng Yu
    <yucheng>
    Hang Su
    Hang Su
    <suhang>
    Jinrui Wang
    Jinrui Wang
    <wangjr>
    Kaiyuan Xu
    Kaiyuan Xu
    <xuky>
    Mengying Wu
    Mengying Wu
    <wumy1>
    Peifan Li
    Peifan Li
    <lipf>
    Peihao Wang
    Peihao Wang
    <wangph>
    Tianyuan Wu
    Tianyuan Wu
    <wuty>
    Ze Song
    Ze Song
    <songze>
    Zhongyi Cai
    Zhongyi Cai
    <caozhy>
    Zhongyue Lin
    Zhongyue Lin
    <linzhy>

    TAs

    Subtitle TAs.
    Ge Yaoxin
    Ge Yaoxin
    Wang Rui
    Wang Rui
    Yuan Yijun
    Yuan Yijun
    Zhang Ge
    Zhang Ge

    Syllabus

    Check the syllabus for the CA course on egate.

    Textbook

    P&H
    Patterson, David A. and Hennessy, John L. Computer Organization and Design RISC-V edition. Morgan Kaufmann.

    References

    K&R
    Kernighan, Brian W. and Ritchie, Dennis M. The C Programming Language (2rd ed.). Prentice Hall.

    Requirements

    Reading
    Read the chapters before class. I will not read the textbook to you during class. Rather, I will help you better understand certain materials in the textbook.
    Class participation
    Participate actively in the discussions both in class and on the forum.
    Communication
    Read your email and the forum at least once in any 12 hour period (including weekends and holidays), as I may post important announcements.

    Grading

    The Engineering Design course consists of projects done in parallel to the Computer Architecture course. The projects thus contribute 33% to your overall score. Neither CA nor the project can be taken without the other.

    Resources

    Feedback

    We always welcome any feedback on what we could do better. You are also welcome to send us feedback anonymously if you like.